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1/21 www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. high reliability serial eeproms i 2 c bus br24 family br24t series description br24t - w series is a serial eeprom of i 2 c bus interface method features 1) completely conforming to the world standard i 2 c bus. all controls available by 2 ports of serial clock (scl) and serial data(sda) 2) other devices than eeprom can be connected to the same port, saving microcontroller port 3) 1.7v 5.5v single power source action most suitable for battery use 4) 1.7v 5.5vwide limit of action voltage, possible fast mode 400khz action 5) page write mode useful for initia l value write at factory shipment 6) auto erase and auto end function at data write 7) low current consumption 8) write mistake prevention function write (write protect) function added write mistake prevention function at low voltage 9) dip-t8/sop8/sop-j8/ssop-b8/tssop-b8/t ssop-b8j/msop8/vson008x2030 various packages 10) data rewrite up to 1,000,000 times 11) data kept for 40 years 12) noise filter built in scl / sda terminal 13) shipment data all address ffh br24t series capacity bit format type power source voltage dip-t8 sop8 sop-j8 ssop-b8 tssop-b8 tssop-b8j msop8 vson008 x2030 1kbit 1288 br24t01-w 1.7 5.5v 2kbit 2568 br24t02-w 1.7 5.5v 4kbit 5128 br24t04-w 1.7 5.5v 8kbit 1k8 br24t08-w 1.7 5.5v 16kbit 2k8 br24t16-w 1.7 5.5v 32kbit 4k8 br24t32-w 1.7 5.5v 64kbit 8k8 br24t64-w 1.7 5.5v 128kbit 16k8 br24t128-w 1.7 5.5v 256kbit 32k8 br24t256-w 1.7 5.5v 512kbit 64k8 BR24T512-W 1.7 5.5v 1024kbit 128k8 br24t1m-w 1.7 5.5v : developing no.11001eat21
technical note 2/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. absolute maximum ratings (ta=25 ) memory cell characteristics (ta=25 , vcc=1.7 5.5v) parameter symbol ratings unit impressed voltage v cc -0.3 +6.5 v permissible dissipation pd 450 (sop8) *1 mw 450 (sop-j8) *2 300 (ssop-b8) *3 330 (tssop-b8) *4 310 (tssop-b8j) *5 310 (msop8) *6 300 (vson008x2030) *7 800 (dip-t8) *8 storage temperature range ts t g 65 +150 action temperature range topr 40 +85 terminal voltage \ -0.3 vcc+1.0 *9 v junction temperature *10 tjmax 150 *1,*2 when using at ta=25 or higher 4.5mw to be reduced per 1 . *3,*7 when using at ta=25 or higher 3.0mw to be reduced per 1 . *4 when using at ta=25 or higher 3.3mw to be reduced per 1 . *5, *6 when using at ta=25 or higher 3.1mw to be reduced per 1 . *8 when using at ta=25 or higher 8.1mw to be reduced per 1 . *9 the max value of terminal voltage is not over 6.5v. when the pulse width is 50ns or less, the min value of terminal voltage is not under -1 .0v. (br24t16/32/64/128/256/512/1m-w) the min value of terminal voltage is not under -0.8v. (br24t01/02/04/08-w) *10 junction temperature at the storage condition. parameter limits unit min. typ. max number of data rewrite times *1 1,000,000 times data hold years *1 40 years *1not 100% tested recommended operating conditions parameter symbol ratings unit power source voltage vcc 1.7 5.5 v input voltage v in 0 vcc electrical characteristics ( unless otherwise specified, ta= 40 +85 , vcc=1.7 5.5v ) parameter symbol limits unit conditions min. typ. max. ?h? input voltage 1 v ih1 0.7vcc vcc+1.0 v ?l? input voltage 1 v il1 -0.3 *2 0.3vcc v ?l? output voltage 1 v ol1 0.4 v i ol =3.0ma, 2.5v Q vcc Q 5.5v (sda) ?l? output voltage 2 v ol2 0.2 v i ol =0.7ma, 1.7v Q vcc 2.5v (sda) input leak current i li 1 1 a v in =0 vcc output leak current i lo 1 1 a v out =0 vcc (sda) current consumption at action i cc1 2.0 ma vcc=5.5v,f scl =400khz, t wr =5ms, byte write, page write br24t01/02/04/ 08/16/32/64-w 2.5 vcc=5.5v,f scl =400khz, t wr =5ms, byte write, page write br24t128/256-w 4.5 vcc=5.5v,f scl =400khz, t wr =5ms, byte write, page write br24t512/1m-w i cc2 0.5 ma vcc=5.5v,f scl =400khz random read, current read, sequential read br24t01/02/04/08/16/ 32/64/128/256-w 2.0 vcc=5.5v,f scl =400khz random read, current read, sequential read br24t512/1m-w standby current i sb 2.0 a vcc=5.5v, sda ? scl=vcc a0,a1,a2=gnd,wp=gnd br24t01/02/04/08/16/ 32/64/128/256-w 3.0 vcc=5.5v, sda ? scl=vcc a0, a1, a2=gnd, wp=gnd br24t512/1m-w radiation resistance design is not made. *1 br24t512/1m-w is a target va lue because it is developing. *2 when the pulse width is 50ns or less, it is -1.0v. (br24t16/ 32/64/128/256/512/1m-w) when the pulse width is 50ns or less , it is -0.8v. (br24t01/02/04/08-w)
technical note 3/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. action timing characteristics (unless otherwise specified, ta= 40 +85 , vcc=1.7 5.5v) parameter symbol limits unit min. typ. max. scl frequency fscl 400 khz data clock ?high? time thigh 0.6 s data clock ?low? time tlow 1.2 s sda, scl rise time *1 tr 1.0 s sda, scl fall time *1 tf 1.0 s start condition hold time thd:sta 0.6 s start condition setup time tsu:sta 0.6 s input data hold time thd:dat 0 ns input data setup time tsu:dat 100 ns output data delay time tpd 0.1 0.9 s output data hold time tdh 0.1 s stop condition setup time tsu:sto 0.6 s bus release time before transfer start tbuf 1.2 s internal write cycle time twr 5 ms noise removal valid period (sda, scl terminal) ti 0.1 s wp hold time thd:wp 1.0 s wp setup time tsu:wp 0.1 s wp valid time thigh:wp 1.0 s *1 not 100% tested. condition input data level: vil=0.2vcc vih=0.8vcc input data timing refarence level: 0.3vcc/0.7vcc output data timing refarence level: 0.3vcc/0.7vcc rise/fall time : Q 20ns sync data input / output timing input read at the rise edge of scl data output in sync with the fall of scl fig.1-(a) sync data input / output timing fig.1-(b) start-stop bit timing fig.1-(c) write cycle timing fig.1-(d) wp timing at write execution fig.1-(e) wp timing at write cancel scl sda (input) sda (output) tr tf thigh tsu:dat tlow thd:dat tdh tpd tbuf 70% 70% 30% 70% 70% 30% 30% 70% 70% 30% 70% 70% 70% 70% 30% 30% 30% 70% 70% tsu:sta thd:sta start condition tsu:sto stop condition 30% 30% 70% 70% d0 ack twr write data (n-th address) start condition stop condition 70% 70% data(1) d0 ack d1 data(n) ack twr 30% 70% stop condition thd:wp tsu:wp 30% 70% data(1) d0 d1 ack data(n) ack thigh:wp 70% 70% twr 70%
technical note 4/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. block diagram fig.2 block diagram pin assignment and description terminal name input/ output br24t01-w br24t02-w br24t 04-w br24t08-w br24t16-w br24t32/64/ 128/256/512-w br24t1m-w a0 input slave address setting don?t use* slave address setting don?t use* a1 input slave address setting don?t use* slave address setting a2 input slave address setting don?t use* slave address setting gnd reference voltage of all input / output, 0v sda input/ output serial data input serial data output scl input serial clock input wp input write protect terminal vcc connect the power source. *pins not used as device address may be se t to any of ?h?, 'l', and 'hi-z'. characteristic data (the following values are typ. ones.) 0 1 2 3 4 5 6 0123456 supply voltage : vcc(v) h input voltage : v ih1 (v) 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supplyvoltage : vcc(v) input leak current : i li (ua) 0 0.2 0.4 0.6 0.8 1 0123456 l output current : i ol (ma) l output voltage : v ol2 (v) 0 0.2 0.4 0.6 0.8 1 1.2 0123456 supply voltage : vcc(v) output leak current : i lo (ua) 0 0.2 0.4 0.6 0.8 1 0123456 l output current : i ol (ma) l output voltage : v ol1 (v) fig.5 'l' output voltage v ol1 -i ol (vcc=1.7v) 0 1 2 3 4 5 6 0123456 supply voltage : vcc(v) l input voltage : v il1 (v) fig.6 'l' output voltage v ol2 -i ol (vcc=2.5v) fig.7 input leak current i li (a0,a1,a2,scl,wp) fig.8 output leak current i lo (sda) fig.4 'l' input voltage v il1 (a0,a1,a2,scl,sda,wp) fig.3 'h' input voltage v ih1 (a0,a1,a2,scl,sda,wp) ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 spec spec spec spec spec spec 8 7 6 5 4 3 2 1 sda scl wp vcc gnd a2 a1 a0 address decoder word address register data register control circuit high voltage generating circuit p ower source voltage detection 8bit ack start stop 1kbit 1024kbit eeprom array *1 *1 *2 *2 *2 13bit 14bit 15bit 16bit 17bit 7bit 8bit 9bit 10bit 11b it 12bit * 1 7bit: br24t01-w 8bit: br24t02-w 9bit: br24t04-w 10bit: br24t08-w 11bit: br24t16-w 2 5 6 vcc scl gnd br24t01-w br24t02-w br24t04-w br24t08-w br24t16-w br24t32-w br24t64-w br24t128-w br24t256-w BR24T512-W br24t1m-w 1 3 4 7 8 wp sda a2 a1 a0 12bit: br24t32-w 13bit: br24t64-w 14bit: br24t128-w 15bit: br24t256-w 16bit: BR24T512-W 17bit: br24t1m-w *2 a0= don't use : br24t04-w, br24t1m-w a0, a1=don't use: br24t08-w a0, a1, a2=don't use: br24t16-w
technical note 5/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. characteristic data (the following values are typ. ones.) 0 0.5 1 1.5 2 2.5 3 3.5 0123456 supply voltage : vcc(v) current consumption at writing : icc1(ma) 0 0.5 1 1.5 2 2.5 0123456 supply voltage : vcc(v) stanby current : i sb (ua) -0.1 0.1 0.3 0.5 0.7 0.9 1.1 0123456 supply voltage : vcc(v) start condition set up time : tsu:sta(us) 0.1 1 10 100 1000 10000 0123456 supply voltage : vcc(v) scl frequency : f?h z -200 -150 -100 -50 0 50 0123456 supply voltage : vcc(v) input data hold time : t hd: sta (ns) 0 0.2 0.4 0.6 0.8 1 0123456 supply voltage : vcc(v) data clk h time : t high (us) 0 0.5 1 1.5 2 2.5 0123456 supply voltage : vcc(v) current consumption at writing : icc1(ma) fig.9 current consumption at write operation i cc 1 (fscl=400khz br24t01/02/04/08/16/32/64-w) fig.10 current consumption at write operation icc1 (fscl=400khz br24t128/256-w) fig.14 stanby operation i sb ( fscl=400khz br24t01/02/04/08/16/32/64/128/256-w ) fig.17 data clock high period t high 0 0.3 0.6 0.9 1.2 1.5 0123456 supply voltage : vccv clk l time : t low (us) fig.18 data clock low period t low 0 0.2 0.4 0.6 0.8 1 0123456 supply voltage : vcc(v) start condition hold time : t hd : sta (us) fig.19 start condition hold time t hd : sta fig.20 start condition setup time t su : sta fig.21 input data hold time t hd : dat high fig.22 input data hold time hd : dat (low fig.23 input data setup time su: dat (high) -200 -150 -100 -50 0 50 0123456 supply voltage : vcc(v) input data hold time : t hd :dat (ns) -200 -100 0 100 200 300 0123456 supply voltage : vcc(v) input data set up time : t su: dat (ns) fig.16 scl frequency f scl fig.12 current consumption at read operation i cc 2 (fscl=400khz br24t01/02/04/08/16/32/64/128/256-w) 0 1 2 3 4 5 6 0123456 supply voltage : vcc(v) current consumption at writing : icc1(ma) fig.11 current consumption at write operation icc1 (fscl=400khz br24t512/1m-w) 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 supply voltage : vcc(v) current consumption at reading : icc2(ma) fig.13 current consumption at read operation i cc 2 (fscl=400khz br24t512/1m-w) fig.15 stanby operation i sb (fscl=400khz br24t512/1m-w) 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 supply voltage : vcc(v) current consumption at reading : icc2(ma) 0 0.5 1 1.5 2 2.5 0123456 supply voltage : vcc(v) stanby current : i sb (ua) ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 spec spec spec spec spec spec spec spec spec spec spec spec the plan for inserting data. (br24t512/1m-w) the plan for inserting data. (br24t512/1m-w) the plan for inserting data. (br24t512/1m-w)
technical note 6/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. characteristic data (the following values are typ. ones.) 0 0.5 1 1.5 2 0123456 supply voltage : vcc(v) bus open time before transmission : t buf (us) 0 1 2 3 4 5 6 0123456 supply voltage : vcc(v) internal writing cycle time : t wr (ms) -200 -100 0 100 200 300 0123456 supply voltage : vcc(v) input data set up time : t su : dat (ns) 0.0 0.5 1.0 1.5 2.0 0123456 supply voltage : vcc(v) output data delay time : t pd (us) fig.24 input data setup time t su : dat (low) fig.25 ' l ' data output delay time t pd 0 fig.26 'h' data output delay time pd 1 fig.28 bus open time before transmission buf fig.29 internal writing cycle time wr 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 supply voltage : vcc(v) noise reduction efective time : t l (scl h) (us) fig.30 noise reduction efection time t l scl h fig.31 noise reduction efective time t l scl l 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 supply voltage : vcc(v) noise reduction efective time : t l (scl l)(us) fig.32 noise resuction efecctive time sda h 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 supply volatge : vcc(v) noise reduction efective time : t l (sda h)(us) fig.33 noise reduction efective time t l sda l 0 0.1 0.2 0.3 0.4 0.5 0.6 0123456 supply voltage : vcc(v) noise reduction effective time : t l (sad l)(us) fig.35 wp setup time t su : wp -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0123456 supply voltage : vcc(v) wp set up time : t su : wp (us) fig.36 wp efective time t high : wp 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0123456 supplyvoltage : vcc(v) wp effective time : t high : wp (us) ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 spec spec spec spec spec spec spec spec spec spec 0.0 0.5 1.0 1.5 2.0 0123456 supply voltage : vcc(v) output data delay time : t pd (us) spec spec -0.5 0.0 0.5 1.0 1.5 2.0 0123456 supply voltage : vcc(v) stop condition setup time : t su :sto(us) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0123456 supplyvoltage : vcc(v) wp data hold time : t hd : wp (us) fig.27 stop condition setup time su :sto ta=-40 ta=25 ta=85 ta=-40 ta=25 ta=85 spec fig.34 wp data hold time thd:wp spec ta=-40 ta=25 ta=85 spec ta=-40 ta=25 ta=85
technical note 7/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. i 2 c bus communication i 2 c bus data communication i 2 c bus data communication starts by start condition input, and ends by stop condition input. data is always 8bit long, and acknowledge is always required after each byte. i 2 c bus carries out data transmission with plural devices connected by 2 communication lines of serial data (sda) and serial clock (scl). among devices, there are ?master? that generates clock and control communication start and end, and ?slave? that is controlled by address peculiar to devices. eeprom becomes ?slave?. and the device that outputs data to bus during data communication is called ?transmitter?, and the dev ice that receives data is called ?receiver?. start condition (start bit recognition) ? before executing each command, start condition (start bit) where sda goes from 'high' down to 'low' when scl is 'high' is necessary. ? this ic always detects whether sda and scl are in start conditi on (start bit) or not, therefor e, unless this confdition is satisfied, any command is executed. stop condition (stop bit recongnition) ? each command can be ended by sda rising from 'low' to 'high' when stop condition (stop bit), namely, scl is 'high' acknowledge (ack) signal ? this acknowledge (ack) signal is a software rule to show whether data transfer has been made normally or not. in master and slave, the device (-com at slave address inpu t of write command, read command, and this ic at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. ? the device (this ic at slave address input of write command, read command, and -com at data output of read command) at the receiver (receiving) side sets sda 'low' during 9 clock cycles, and outputs acknowledge signal (ack signal) showing that it has received the 8bit data. ? this ic, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ack signal) 'low'. ? each write action outputs acknowledge signal (ack signal) 'l ow', at receiving 8bit data (word address and write data). ? each read action outputs 8bit data (read data), and detec ts acknowledge signal (ack signal) 'low'. when acknowledge signal (ack signal) is detected, and stop condition is not sent from the mast er (-com) side, this ic continues data output. when acknowledge signal (ack signal) is not detected, this ic stops data transfer, and recognizes stop cindition (stop bit), and ends read action. and this ic gets in status. device addressing ? output slave address after start condition from master. ? the significant 4 bits of slave address are used for recognizing a device type. the device code of this ic is fixed to '1010'. ? next slave addresses (a2 a1 a0 --- device address) are for se lecting devices, and plural ones can be used on a same bus according to the number of device addresses. ? the most insignificant bit (r/w --- read / write ) of slave address is used for designating write or read action, and is as shown below. setting w / r to 0 ------- write (setting 0 to word address setting of random read) setting w / r to 1 ------- read type slave address maximum number of connected buses br24t01-w,br24t02-w 1 0 1 0 a2 a1 a0 r/ w DD 8 br24t04-w 1 0 1 0 a2 a1 p0 r/ w DD 4 br24t08-w 1 0 1 0 a2 p1 p0 r/ w DD 2 br24t16-w 1 0 1 0 p2 p1 p0 r/ w DD 1 br24t32-w,br24t64-w,br24t128-w, br24t256-w,BR24T512-W 1 0 1 0 a2 a1 a0 r/ w DD 8 br24t1m-w 1 0 1 0 a2 a1 p0 r/ w DD 4 p0 p2 are page select bits. 89 89 89 s p condition condition ack stop ack data data addres s start r/w ack 1-7 sda scl 1-7 1-7 fig.37 data transfer timing
technical note 8/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. write command write cycle ? arbitrary data is written to eeprom. when to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is po ssible by page write cycle. the maximum number of write bytes is specified per device of each capacity. up to 25 6 arbitrary bytes can be written.(in the case of br24t1m-w) w r i t e s t a r t r / w a c k s t o p word address(n) data(n) sda line a c k a c k data(n+15) a c k slave address 1 0 0 1a0 a1 a2 wa 7 d0 d7 d0 ? ) wa 0 a1 a2 wa 7 d7 1 1 0 0 w r i t e s t a r t r / w s t o p word address data slave address a0 wa 0 d0 a c k sda line a c k a c k note) fig.38 byte write cycle (br24t01/02/04/08/16-w) a1 a2 wa 14 1 1 0 0 w r i t e s t a r t r / w s t o p 1st word address data slave address a0 d0 a c k sda line a c k a c k note) wa 13 wa 12 wa 11 wa 0 a c k 2nd word address d7 *1 wa 15 *1 as for wa12, br24t32-w becomes don't care. as for wa13, br24t32/64-w becomes don't care. as for wa14, br24t32/64/128-w becomes don't care. as for wa15, br24t32/64/128/256-w becomes don't care. fig.39 byte write cycle (br24t32/64/128/256/512/1m-w) fig.40 page write cycle (br24t01/02/04/08/16-w) fig.41 page write cycle (br24t32/64/128/256/512/1m-w) *1 as for wa12, br24t32-w becomes don't care. as for wa13, br24t32/64-w becomes don't care. as for wa14, br24t32/64/128-w becomes don't care. as for wa15, br24t32/64/128/256-w becomes don't care. *2 as for br24t128/256-w becomes (n+63) as for BR24T512-W becomes (n+127) as for br24t1m-w becomes (n+255) w r i t e s t a r t r / w a c k s t o p 1st word a ddress(n) sda line a c k a c k data(n+31) a c k slave a ddress 1 0 0 0 1 0 a 0 a 1 a 2 wa 14 d0 ? ) *1 data(n) d0 d7 a c k 2nd word a ddress(n) wa 0 wa 13 wa 12 wa 11 *2 note) fig.42 difference of slave address of each type as for wa7, br24t01-w becomes don't care. *1 as for wa7, br24t01-w becomes don't care. *2 as for br24t01/02-w becomes (n+7) *2 *1 wa 15 *1 in br24t16-w, a2 becomes p2. *2 in br24t08/16-w, a1 becomes p1. *3 in br24t04/08/16/1m-w a0 becomes p0. 1 0 0 1a0 a1 a2 *1 *2 *3
technical note 9/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. ? during internal write execution, all input comm ands are ignored, therefore ack is not sent back. ? data is written to the address designated by word address (n-th address) ? by issuing stop bit after 8bit data input, write to memory cell inside starts. ? when internal write is started, command is not accepted for twr (5ms at maximum). ? by page write cycle, the following can be written in bulk : up to 8byte (br24t01-w, br24t02-w) up to 16byte (br24t04-w, br24t08-w, br24t16-w) up to 32byte (br24t32-w, br24t64-w) up to 64byte (br24t128-w, br24t256-w) up to 128byte (BR24T512-W) up to 256byte (br24t1m-w) and when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (refer to "internal address increment" of "notes on page write cycle" in p10.) ? as for page write cycle of br24t01-w and br24t02-w, after the significant 4 bits (in the case of br24t01-w) of word address, or the significant 5 bits (in t he case of br24t02-w) of word address ar e designated arbitrarily, by continuing data input of 2 bytes or more, the addre ss of insignificant 3 bits is incremented internally, and data up to 8 bytes can be written. ? as for page write command of br24t04-w, br24t08-w and br24t16-w, after page select bit ?p0?(in the case of br24t04-w), after page select bit ?p0,p1?(in the case of br 24t08-w), after page select bit ?p0,p1,p2?(in the case of br24t16-w) of slave address are designat ed arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented internally, and data up to 16 bytes can be written. ? as for page write cycle of br24t32-w and br24t64-w, after the significant 7 bits (in the case of br24t32-w) of word address, or the significant 8 bits (in t he case of br24t64-w) of word address ar e designated arbitrarily, by continuing data input of 2 bytes or more, the addre ss of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written. ? as for page write cycle of br24t128-w and br24t256-w, after t he significant 8 bits (in the case of br24t128-w) of word address, or the significant 9 bits (in the case of br24t256-w) of word address are designated arbitrarily, by continuing data input of 2 bytes or mo re, the address of insignificant 6 bits is incremented internally, and data up to 64 bytes can be written. ? as for page write cycle of BR24T512-W after the significant 9 bi ts of word address is designated arbitrarily, by continuing data input of 2 bytes or more, the addre ss of insignificant 7 bits is incremented internally, and data up to 128 bytes can be written. ? as for page write cycle of br24t1m-w after page select bit ?p0? and the significant 8 bit of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 8 bits is incremented internally, and data up to 256 bytes can be written.
technical note 10/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. notes on page write cycle list of numbers of page write number of pages 8byte 16byt e 32byte 64byte 128byte 256byte product number br24t01-w br24t02-w br24t04-w br24t08-w br24t16-w br24t32-w br24t64-w br24t128-w br24t256-w BR24T512-W br24t1m-w the above numbers are maximum bytes for respective types. any bytes below these can be written. in the case br24t256-w, 1 page=64bytes, but the page write cycle time is 5ms at maximum for 64byte bulk write. it does not stand 5ms at maximum 64byte=320ms(max.) internal address increment page write mode (in the case of br24t16-w) write protect (wp) terminal ? write protect (wp) function when wp terminal is set vcc (h level), data rewrite of all addr esses is prohibited. when it is set gnd (l level), data rewrite of all address is enabled. be sure to connect this termina l to vcc or gnd, or control it to h level or l level. do not use it open. in the case of use it as an rom, it is re commended to connect it to pull up or vcc. at extremely low voltage at power on / off, by setti ng the wp terminal 'h', mistake write can be prevented. for example, when it is started from address 0eh, therefore, increment is made as below, 0eh 0fh 00h 01h ??? which please note. 0eh ??? 0e in hexadecimal, therefore, 00001110 becomes a binary number. wa7 wa4 wa3 wa2 wa1 wa0 0 00000 0 00001 0 00010 0 01110 0 01111 0 00000 increment 0eh significant bit is fixed. no digit up
technical note 11/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. read command read cycle data of eeprom is read. in read cycle, there are random read cycle and current read cycle. random read cycle is a command to read data by designating address, and is used gener ally. current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. in both the read cycles, sequential read cycle is available, and the next address data can be read in succession. ? in random read cycle, data of designated word address can be read. ? when the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-t h address, i.e., data of t he (n+1)-th address is output. ? when ack signal 'low' after d0 is detected, and stop conditi on is not sent from master (-com) side, the next address data can be read in succession. ? read cycle is ended by stop condition where 'h' is input to ack signal after d0 and sda signal is started at scl signal 'h' . ? when 'h' is not input to ack signal after d0, seque ntial read gets in, and the next data is output. therefore, read command cycle cannot be ended. when to end read command cycle, be sure input stop condition to input 'h' to ack signal after d0, and to start sda at scl signal 'h'. ? sequential read is ended by stop condition where 'h' is input to ack signal after arbitrary d0 and sda is started at scl signal 'h'. fig.43 random read cycle (br24t01/02/04/08/16-w) fig.44 random read cycle (br 24t32/64/128/25 6/512/1m-w) *1 as for wa12, br24t32-w become don?t care. as for wa13, br24t32/64-w become don?t care. as for wa14, br24t32/64/128-w become don?t care. as for wa15, br24t32/64/128/256-w become don?t care. fig.45 current read cycle fig.46 sequential read cycle (in the case of current read cycle) *1 in br24t16-w, a2 becomes p2. *2 in br24t08/16-w, a1 becomes p1. *3 in br24t08/16/1m-w, a0 becomes p0. note) *1 as for wa7,br24t01-w become don?t care. fig.47 difference of slave address of each type a2 a0 a1 a1 a2 w r i t e s t a r t r / w a c k s t o p 1st word address a0 d7 d0 2nd word address(n) a c k s t a r t slave address 1 0 0 1 r / w r e a d wa 0 note) *1 wa 15 wa 14 wa 13 wa 12 wa 11 w r i t e s t a r t r / w a c k s t o p word address(n) sda line a c k a c k data(n) a c k slave address 10 0 1 a0 a1 a2 wa 7 a0 d0 slave address 10 0 1a1 a2 s t a r t d7 r / w r e a d wa 0 note) *1 s t a r t s t o p sda line a c k data(n) a c k slave address 10 0 1 a0 a1 a2 d0 d7 r / w r e a d note) r e a d s t a r t r / w a c k s t o p data ( n ) sda line a c k a c k data ( n+x ) a c k slave address 10 0 1 a0 a1 a2 d0 d7 d0 d7 note *1 as for wa12, br24t32-w becomes don't care. as for wa13, br24t32/64-w becomes don't care. as for wa14, br24t32/64/128-w becomes don't care. as for wa15, br24t32/64/128/256-w becomes don't care. *2 as for br24t128/256-w becomes (n+63) as for BR24T512-W becomes (n+127) as for br24t1m-w becomes (n+255) *1 as for wa7, br24t01-w becomes don't care. *2 as for br24t01/02-w becomes (n+7) 1 0 0 1a0 a1 a2 *1 *2 *3
technical note 12/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. software reset software reset is executed when to avoid malfunction after po wer on, and to reset during command input. software reset has several kinds, and 3 kinds of them are shown in the figure below. (refer to fig.48-(a), fig.48-(b), fig.48-(c).) in dummy clock input area, release the sda bus ('h' by pull up) . in dummy clock area, ack output and read data '0' (both 'l' level) may be output from eeprom, therefor e, if 'h' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. acknowledge polling during internal write execution, all input commands are ignored , therefore ack is not sent ba ck. during internal automatic write execution after write cycle input, next command (slave addre ss) is sent, and if the first ack signal sends back 'l', then it means end of write action, while if it sends back 'h', it means now in writin g. by use of acknowledge polling, next command can be executed without waiting for twr = 5ms. when to write continuously, w / r = 0, when to carry out current read cycle after write, slave address w / r = 1 is sent, and if ack signal sends back 'l', then execute wo rd address input and data output and so forth. 1 2 13 14 scl dummy clock14 start2 scl fig.48-(a) the case of dummy clock +start+start+ command input start command from start input. 2 1 8 9 dummy clock 9 start fig.48-(b) the case of start +9 dummy clocks +start+ command input start normal command normal command normal command normal command start 9 sda sda scl sd 1 2 3 8 9 7 fig.48-(c) start9+ command input normal command normal command sda slave address word address s t a r t first write command a c k h a c k l slave address slave address slave address data write command during internal write, ack = high is sent back. after completion of internal write, ack=low is sent back, so input next word address and data in succession. twr twr second write command s t a r t s t a r t s t a r t s t a r t s t o p s t o p a c k h a c k h a c k l a c k l fig.49 case to continuously write by acknowledge polling
technical note 13/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. wp valid timing (write cancel) wp is usually fixed to 'h' or 'l', but when wp is used to canc el write cycle and so forth, pay attention to the following wp valid timing. during write cycle execution, in cancel valid area, by setting wp='h', write cycle can be cancelled. in both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in d0 of data(in page write cycle, the first byte data) is cancel invalid area. wp input in this area becomes don't care. the area from the rise of scl to take in d0 to i nput the stop condition is cancel valid area. and, after execution of forced end by wp, standby status gets in. command cancel by start condition and stop condition during command input, by continuously inputting start condit ion and stop condition, command can be cancelled. (fig.51) however, in ack output area and during data read, sda bus ma y output 'l', and in this case, start condition and stop condition cannot be input, so reset is not available. therefore, execute software reset. and when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out curre nt read cycle in succession. when to carry out read cycle in succession, carry out random read cycle. ? rise of d0 taken clock scl d0 ack enlarged view scl sda ack d0 ? rise of sda sda wp wp cancel invalid area wp cancel valid area data is not written. fig.50 wp valid timing slave address d7 d6 d5 d4 d3 d2 d1 d0 data twr sda d1 s t a r t a c k l a c k l a c k l a c k l s t o p word address fig.51 case of cancel by start, stop condition during slave address input scl sda 1 1 0 0 start condition stop condition enlarged view wp cancel invalid area
technical note 14/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. i/o peripheral circuit pull up resistance of sda terminal sda is nmos open drain, so requires pull up resistance. as for this resistance value (r pu ), select an appropriate value to this resistance value from microcontroller v il , i l , and v ol -i ol characteristics of this ic. if r pu is large, action frequency is limited. the smaller the r pu , the larger the consumption current at action. maximum value of r pu the maximum value of r pu is determined by the following factors. sda rise time to be determined by the capacitance (cbus) of bus line of r pu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. the bus electric potential a to be determined by input leak total (i l ) of device connected to bus at output of 'h' to sda bus and r pu should sufficiently secure the input 'h' level (v ih ) of microcontroller and eeprom including recommended noise margin 0.2vcc. v cc i l r pu 0.2 v cc R v ih l ih cc pu i v v 8 . 0 r ? ? ? ex.) vcc =3v il=10a vih=0.7 vcc from 6 pu 10 10 3 7 . 0 3 8 . 0 r ? ? ? ? ? ? ? 300 [k ] minimum value of r pu the minimum value of r pu is determined by the following factors. when ic outputs low, it should be satisfied that v olmax =0.4v and i olmax =3ma. ol pu ol cc i r v v ? ? ol ol cc pu i v v r ? ? ? v olmax = should secure the input 'l' level (v il ) of microcontroller and eeprom including recommended noise margin 0.1vcc. v olmax Q v il 0.1 v cc ex.) v cc =3v, v ol =0.4v, i ol =3ma, microcontroller, eeprom v il =0.3vcc from 3 pu 10 3 4 . 0 3 r ? ? ? ? ? 867[ ] and v ol =0.4 v v il =0.3 3 =0.9 v therefore, the condition is satisfied. pull up resistance of scl terminal when scl control is made at cmos output port, there is no need, but in the ca se there is timing where scl becomes 'hi-z', add a pull up resistance. as for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of output port of microcontroller. fig.52 i/o circuit diagram microcontroller r pu a sda terminal i l i l bus line capacity cbus br24txx
technical note 15/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. cautions on microcontroller connection r s in i 2 c bus, it is recommended that sda port is of open drain in put/output. however, when to use cmos input / output of tri state to sda port, insert a series resistance rs betw een the pull up resistance rpu a nd the sda terminal of eeprom. this is controls over current that occurs when pmos of the microcontroller and nmos of eeprom are turned on simultaneously. rs also plays the role of protection of sd a terminal against surge. therefore, even when sda port is open drain input/output, rs can be used. maximum value of rs the maximum value of rs is determined by the following relations. sda rise time to be determined by the capacity (cbus) of bus line of rpu and sda should be tr or below. and ac timing should be satisfied even when sda rise time is late. the bus electric potential a to be determined by rpu and rs the moment when eeprom outputs 'l' to sda bus sufficiently secure the input 'l' level (v il ) of microcontroller including recommended noise margin 0.1vcc. ? ? il cc ol s pu ol cc v v 1 . 0 v r r v v ? ? ? ? ? ? ? pu il cc ol cc s r v v 1 . 1 v v r ? ? ? ? ? ex) v cc =3v v il =0.3v cc v ol =0.4v r pu =20k 3 s 10 20 3 3 . 0 3 1 . 1 3 1 . 0 4 . 0 3 3 . 0 r ? ? ? ? ? ? ? ? ? ? ] k [ 67 . 1 ? minimum value of rs the minimum value of rs is determined by over current at bus collision. when over current flows, noises in power source line, and instantaneous power failure of power source may occur. when allowable over current is defined as i, the following relation must be satisfied. determine the allowable current in consideration of impedance of power source line in set and so forth. set the over current to eeprom 10ma or below. i r v s cc ? i v r cc s ? ? ex) v cc =3v i=1ma ] [ 300 10 10 3 r 3 s ? ? ? ? r pu microcontroller r s eeprom fig.53 i/o circuit diagram fig.54 i nput / output co llision timing a ck 'l' output of eeprom 'h' output of microcontroller over current flows to sda line by 'h' output of microcontroller and 'l' output of eeprom. scl sda microcontroller eeprom 'l'output r s r pu 'h' output over current i fig.56 i/o circuit diagram fig.55 i/o circuit diagram r pu micro controller r s eeprom i ol a bus line capacity cbus v ol v cc v il
technical note 16/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. i 2 c bus input / output circuit input (a0, a1, a2, scl, wp) input / output (sda) fig.57 input pin circuit diagram fig.58 input / output pin circuit diagram
technical note 17/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. notes on power on at power on, in ic internal circuit and set, vcc rises through unstable low voltage area, and ic inside is not completely reset , and malfunction may occur. to prevent this, functions of po r circuit and lvcc circuit are equipped. to assure the action, observe the following conditions at power on. 1. set sda = 'h' and scl ='l' or 'h? 2. start power source so as to satisfy the recommended conditions of t r , t off , and vbot for operating por circuit. toff tr vbot 0 v cc 3. set sda and scl so as not to become 'hi-z'. when the above conditions 1 and 2 cannot be obs erved, take the following countermeasures. a) in the case when the above condition 1 cannot be observed. when sda becomes 'l' at power on . control scl and sda as shown below, to make scl and sda, 'h' and 'h'. b) in the case when the above condition 2 cannot be observed. after power source becomes stable, execute software reset(p12). c) in the case when the above conditions 1 and 2 cannot be observed. carry out a), and then carry out b). low voltage malfunction prevention function lvcc circuit prevents data rewrite action at low power, and preven ts wrong write. at lvcc voltage (typ. =1.2v) or below, it prevent data rewrite. vcc noise countermeasures bypass capacitor when noise or surge gets in the power source line, malfunc tion may occur, therefore, for removing these, it is recommended to attach a bypass capacitor (0.1f) between ic v cc and gnd. at that moment, atta ch it as close to ic as possible. and, it is also recommended to attach a bypass capacitor between board vcc and gnd. recommended conditions of tr, toff,vbot tr toff vbot 10ms or below 10ms or larger 0.3v or below 100msor below 10msor larger 0.2v or below fig.59 rise waveform diagram fig.60 when scl= 'h' and sda= 'l' fig.61 when scl='l' and sda='l' tlow tsu:dat tdh a fter vcc becomes stable scl v cc sda tsu:dat a fter vcc becomes stable
technical note 18/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. notes for use (1) described numeric values and data are design repr esentative values, and the values are not guaranteed. (2) we believe that application circuit examples are recommendabl e, however, in actual use, confirm characteristics further sufficiently. in the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characterist ics and transition characteristics and fluc tuations of external parts and our lsi. (3) absolute maximum ratings if the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, lsi may be destructed. do not impress voltage and temperat ure exceeding the absolute maximum ratings. in the case of fear exceeding the absolute maximum ratings, take physica l safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to lsi. (4) gnd electric potential set the voltage of gnd terminal lowest at any action condition. make sure that each terminal voltage is lower than that of gnd terminal. (5) terminal design in consideration of permissible loss in actual use cond ition, carry out heat design with sufficient margin. (6) terminal to terminal shortcircuit and wrong packaging when to package lsi onto a board, pay sufficient attentio n to lsi direction and displacement. wrong packaging may destruct lsi. and in the case of shor tcircuit between lsi terminals and terminals and power source, terminal and gnd owing to foreign matter, lsi may be destructed. (7) use in a strong electromagnetic field may cause malfunction, therefore, ev aluate design sufficiently.
technical note 19/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. order part number b r 2 4 t 1 2 8 f v t - w g e 2 part no. bus type 24 i 2 c operating temperature/ power source voltage -40 ~+85 1.7v~5.5v capacity 01=1k 64=64k 02=2k 128=128k 04=4k 256=256k 08=8k 512=512k 16=16k 1m=1024k 32=32k package blank :dip-t8 f :sop8 fj :sop-j8 fv : ssop-b8 fvt : tssop-b8 fvj : tssop-b8j fvm : msop8 nux :vson008x2030 double cell halogen free packaging and forming specification e2: embossed tape and reel (sop8, sop8-j8, ssop-b8, tssop-b8, tssop-b8j) tr: embossed tape and reel (msop8, vson008x2030) none: tube (dip-t8) ? order quantity needs to be multiple of the minimum quantity. tube container quantity direction of feed 2000pcs direction of products is fixed in a container tube (unit : mm) dip-t8 0 ? 15 7.62 0.3 0.1 9.3 0.3 6.5 0.3 85 1 4 0.51min. 3.4 0.3 3.2 0.2 2.54 0.5 0.1 ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin (unit : mm) sop8 0.9 0.15 0.3min 4 + 6 ? 4 0.17 +0.1 - 0.05 0.595 6 4 3 8 2 5 1 7 5.0 0.2 6.2 0.3 4.4 0.2 (max 5.35 include burr) 1.27 0.11 0.42 0.1 1.5 0.1 s 0.1 s ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () direction of feed reel 1pin (unit : mm) sop-j8 4 + 6 ? 4 0.2 0.1 0.45min 234 5 6 7 8 1 4.9 0.2 0.545 3.9 0.2 6.0 0.3 (max 5.25 include burr) 0.42 0.1 1.27 0.175 1.375 0.1 0.1 s s
technical note 20/21 br24t series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. direction of feed reel ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 3000pcs e2 () 1pin (unit : mm) tssop-b8 0.08 s 0.08 m 4 4 234 8765 1 1.0 0.05 1pin mark 0.525 0.245 +0.05 ? 0.04 0.65 0.145 +0.05 ? 0.03 0.1 0.05 1.2max 3.0 0.1 4.4 0.1 6.4 0.2 0.5 0.15 1.0 0.2 (max 3.35 include burr) s direction of feed reel ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand 2500pcs e2 () 1pin (unit : mm) tssop-b8j 0.08 m 0.08 s s 4 4 (max 3.35 include burr) 5 7 8 1234 6 3.0 0.1 1pin mark 0.95 0.2 0.65 4.9 0.2 3.0 0.1 0.45 0.15 0.85 0.05 0.145 0.1 0.05 0.32 0.525 1.1max +0.05 ? 0.03 +0.05 ? 0.04 direction of feed reel ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper right when you hold reel on the left hand and you pull out the tape on the right hand 3000pcs tr () 1pin (unit : mm) msop8 0.08 s s 4.0 0.2 8 3 2.8 0.1 1 6 2.9 0.1 0.475 4 5 7 (max 3.25 include burr) 2 1pin mark 0.9max 0.75 0.05 0.65 0.08 0.05 0.22 +0.05 ? 0.04 0.6 0.2 0.29 0.15 0.145 +0.05 ? 0.03 4 + 6 ? 4
technical note 21/21 br24t -w series www.rohm.com 2011.03 - rev.a ? 2011 rohm co., ltd. all rights reserved. ? order quantity needs to be multiple of the minimum quantity. embossed carrier tape tape quantity direction of feed the direction is the 1pin of product is at the upper right when you hold reel on the left hand and you pull out the tape on the right hand 4000pcs tr () direction of feed reel 1pin (unit : mm) vson008x2030 5 1 8 4 1.4 0.1 0.25 1.5 0.1 0.5 0.3 0.1 0.25 +0.05 ? 0.04 c0.25 0.6max (0.12) 0.02 +0.03 ? 0.02 3.0 0.1 2.0 0.1 1pin mark 0.08 s s
r1120 a www.rohm.com ? 2011 rohm co., ltd. all rights reserved. notice rohm customer support system http://www.rohm.com/contact/ thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact us. notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specied herein is subject to change for improvement without notice. the content specied herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specied in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no responsibility for such damage. the technical information specied herein is intended only to show the typical functions of and examples of application circuits for the produc ts. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, ofce-automation equipment, commu- nication devices, electronic appliances and amusement devices). the products specied in this document are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, re or any other damage caused in the event of the failure of any product, such as derating, redundancy, re control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel- controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specied herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law.

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